1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a structure of a lateral MOSFET.
2. Background Art
There is a lateral MOSFET, as one of the conventional semiconductor devices, that has a middle to high breakdown voltage and operates at a high speed. An example of the structure thereof is as follows.
In a p− type semiconductor substrate, an n+ type source layer and an n+ type drain layer are formed with a predetermined interval. In a region between an n+ type source layer and an n+ type drain layer, as a gate region, a gate electrode is formed via a gate oxide layer. Furthermore, an n− type RESURF (REduced SUFace Field) layer is formed between the gate region and the n+ type drain layer. A lateral MOSFET thus constituted on the purpose of achieving a high speed operation is requested to decrease the capacitance between the gate and the drain. Various kinds of structures are employed to decrease the capacitance between the gate and the drain. However, to employ the various kinds of structures result in causing some problems such as deceasing a breakdown voltage and changing a threshold value of the MOSFET due to the structure of the lateral MOSFET.
Hereinafter, the problems will be specifically described.
As described above, it is necessary to decrease the capacitance between the gate and the drain in the lateral MOSFET. In other words, it is necessary to decrease the overlapping amount or overlapping area formed by the gate region and the drain diffusion layer. In order to satisfy the above requirement, a device should be formed as follows: Under a gate electrode, forming a p type region, the conductivity type of which is opposite to that of an n type RESURF layer or an n+ type drain layer. Then performing an ion implantation in a self-aligned manner using the gate electrode as a mask to form an n− type RESURF layer.
There are following three methods to form the aforementioned structure.
First, there is a method of forming a p type well (or p type base) having an appropriate concentration as a channel region on the entire surface of the device. Generally, the concentration of a p− type semiconductor substrate serving as an active region of the device is in a range of 1×1015 to 1×1016 cm−3, which is rather low as a channel region. Accordingly, sometimes a p type well serving as a channel region and having an appropriate concentration is formed on the entire surface of the device by ion implantation as in the case of a CMOS. Generally, a channel region should have a concentration of from 1×1017 to 1×1018 cm−3. In this structure, however, a PN junction having relatively high concentrations is formed. When a reverse bias is applied, a depletion layer extends in the PN junction portion. However, since the concentration of the p type well is as high as 1×1017 to 1×1018 cm−3, a breakdown is occurred before a sufficient depletion layer is formed. As a result, a breakdown voltage of the device in a device depth direction decreases.
Second, there is a method of forming a p type well (or p type base) only in a source region, and performing p type channel implantation on part of a region under the gate electrode, besides the p type well. Since a channel implantation layer has a concentration of 1×1017 to 1×1018 cm−3, a displacement of a mask for performing a channel implantation affects the threshold value of the device. In order to secure a breakdown voltage at the drain region, the substrate portion should be a p− type semiconductor substrate having a concentration of 1×1015-1×1016 cm−3 or a p− type layer having a similar concentration. Accordingly, a mask displacement of the channel implantation layer having a concentration of 1×1017-1×1018 cm−3 has much effect on the threshold value. If the gate length is relatively long, the ratio of the mask displacement portion is rather small and the effect thereof is not so great. However, as the gate length decreases, the effect thereof reaches a level that cannot be ignored.
Third, there is a method of inserting or forming a channel implantation layer into or on the entire region under a gate electrode. Generally, since a channel implantation layer is a shallow diffusion layer, no high concentration PN junction is formed in an element depth direction in a drain region portion. However, since the channel implantation layer having a concentration of 1×1017-1×1018 cm−3 overlaps the n− type RESURF layer having a concentration of 1×1016-1×1018 cm−3 at the tip portion close to the gate electrode, the concentration of the n− type RESURF layer in this portion extremely decreases. Accordingly, a high resistance component is formed at the portion where the concentration decreases, thereby the ON resistance of the device increases.